As a power switching element, a power metal oxide semiconductor field effect transistor (MOSFET) is widely used. MOSFETs are roughly classified into a planar type using a flat surface on a semiconductor wafer as a channel and a trench gate type using a side surface of a trench formed on a semiconductor wafer surface as a channel. In the trench gate type, reducing the cell pitch can increase the channel width density. This can restrict the ON resistance without increasing the element size. In addition, the structure of the trench gate type itself is suitable to restrict the ON resistance. For example, in a case of a planar type MOSFET having an n channel, a p-type well for the formation of a channel on an n-type drift layer is provided for each cell. One pair of adjacent p-type well sandwich an n-type drift layer to parasitically form a JFET region. In this manner, a planar type MOSFET parasitically has a JFET region between adjacent cells. A resistance component originating from a JFET region, i.e., a JFET resistance, affects the MOSFET so as to increase the ON resistance. Using a trench gate type structure can avoid the formation of a JFET region of the type described above owing to the structure. This can therefore restrict the ON resistance.
On the other hand, in the trench gate type, an electric field tends to concentrate on the bottom surface of a trench extending from the upper surface of a semiconductor wafer to its lower surface, and more intensive electric field concentration can occur due to the shape of a trench bottom portion. This makes a high electric field easily be applied to the gate insulating film on the trench bottom surface. When silicon carbide as a wide band gap semiconductor is applied as a semiconductor material, in particular, an especially high electric field can be applied to the gate insulating film. This is because the high breakdown electric field of silicon carbide is often used to obtain a high withstand voltage, and in this case, a high electric field is applied to the gate insulating film at OFF time of the MOSFET. In this case, consideration needs to be given to the securing of reliability of a gate insulating film, typically a gate oxide film.
For example, Japanese Patent Application Laid-Open No. 2012-238887 (Patent Document 1) discloses a metal oxide semiconductor field effect transistor (MOSFET) having a trench gate structure as a silicon carbide semiconductor device. This MOSFET has a p+ layer in contact with an n-type drift layer on the bottom portion of a trench. This relaxes the electric field applied to a gate insulating film at OFF time of the MOSFET. The MOSFET is also provided with an n-type current diffusion layer that is formed between a p-type base layer and an n-type drift layer and has an impurity concentration higher than that of the n-type drift layer. The n-type current diffusion layer diffuses a current path in the lateral direction of an element to relax the concentration of a current path in the n-type drift layer onto near the trench. This reduces the ON resistance of the MOSFET.